The escalating demands for high density and performance associated with non-volatile memory devices, such as electrically erasable programmable read only memory (EEPROM) devices, require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology. For example, the reduction of design features makes it difficult for the memory device to meet its expected data retention requirement.
In addition, various backend processes that are used to complete the formation of a working memory device often create problems associated with the operation of the memory device. For example, backend of line (BEOL) conductive interconnects, such as copper interconnects, often suffer from poor reliability due to, for example, electromigration. These problems often result in poor overall performance for the memory device and, ultimately, may lead to device failure.